Semiconductor device

ABSTRACT

An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode  16,  a source electrode  15  and a drain electrode  17  are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

FIELD OF THE INVENTION

[0001] The present invention relates to a field effect transistor (FET)with a sapphire substrate, in particular to a field effect transistorutilizing a group III nitride semiconductor material such as GaN.

BACKGROUND TO THE INVENTION

[0002] The group III nitride semiconductors including GaN have carriertransport characteristics close to that of GaAs, together with highbreakdown electric fields due to their wide band gaps. They are, thus,regarded as strong candidate materials for high frequency, high powertransistors.

[0003] When a device is manufactured making use of a GaN basedsemiconductor material, because it is difficult to obtain a bulk GaNbased substrate, there is normally employed a method of fabricating adevice wherein a GaN based semiconductor layer is formed by epitaxialgrowth on a substrate of a different material. For the substrate of adifferent material, sapphire or SiC is utilized. SiC has an excellentthermal conductivity but also drawbacks of high cost and difficulty toattain a large wafer area. In contrast, although sapphire has aninferior thermal conductivity, the cost can be lowered through the useof a wafer with a larger diameter. In application, therefore, thesesubstrates of different materials are chosen appropriately, according tothe use and the purpose for utilizing and so forth. In the field ofMMICs (Monolithic Microwave Integrated Circuits) or the likes, there aresome applications with small electric power in which the restriction forheat dissipation is not strong. In such applications, sapphire ratherthan SiC is in wide use. When, using a sapphire substrate, a FET isfabricated, in prior art, a C plane sapphire is utilized and the deviceis formed on the C plane (see Japanese Patent Application Laid-open, No.82671/2000, Jpn. J. Appl. Phys., Vol. 38 (1999) pp. 2630 (T. Egawa etal.) and so on). FIG. 5 is a view showing a structure of a conventionalMESFET (Metal Semiconductor FET) disclosed in FIG. 12 of Japanese PatentApplication Laid-open, No. 82671/2000. Herein, upon a C plane sapphiresubstrate 51, a GaN buffer layer 52 and an n-type GaN channel layer 53are laid, and a source electrode 54, a gate electrode 55 and a drainelectrode 56 are formed thereon. Meanwhile, FIG. 6 is a view showing astructure of a conventional HEMT (High Electron Mobility Transistor)disclosed in FIG. 13 of the same publication. Upon a C plane sapphiresubstrate 61, a GaN buffer layer 62, a non-doped GaN channel layer 63and an n-AlGaN electron supplying layer 64 are laid, and a sourceelectrode 65, a gate electrode 66 and a drain electrode 67 are formedthereon. In both of these, a GaN based semiconductor layer is laid upona C plane of sapphire to fabricate a FET. Further, it is described, inthat publication, that any plane of sapphire such as an A plane, Nplane, S plane, R plane, M plane or the like can be utilized infabricating an optical device or an electronic device with a sapphiresubstrate. However, examples specifically disclosed therein are nothingelse but the ones of forming a device on a C plane of sapphire, and anyspecific manufacturing methods or device design criteria for the casesto utilize any other plane are not described at all.

[0004] As described above, in conventional techniques, a GaN basedsemiconductor layer is formed upon a C plane of sapphire to form adevice, which gives rise to the following problems.

[0005] First, attempts to obtain a wafer with a larger diameter arelimited to a certain extent. In recent years, from the point of view ofimproving productivity, there have been demands that wafers should havelarger diameters. Yet, the sapphire whose C plane is chosen for thecrystal growth plane cannot be readily made to have a larger diameter,because of its low workability through surface polishing due to its poormechanical processing feasibility and little ability to grow the crystalto have a large width by the ribbon crystal method or the like. Asubstrate with the largest diameter attained so far is 4 inches indiameter.

[0006] Secondly, a heat radiation characteristic thereof is difficult toimprove. Since sapphire has a low thermal conductivity, improvements onthe heat radiation characteristic have been sought after for some timeand, for this purpose, thinner substrates have been looked for.Nevertheless, sapphire has insufficient feasibility in mechanicalprocessing as described above so that a reduction in thickness is hardto achieve and, thus, the heat radiation characteristic is difficult toimprove.

[0007] Thirdly, parasitic capacitances generated in the substrate arerelatively large and act as an inhibitory factor to the improvement ofdevice performance. Especially, in the case of a C plane sapphire, it isnecessary to make the substrate have a certain thickness from the pointof mechanical processing feasibility, which results in generation oflarge parasitic capacitances in the substrate.

SUMMARY OF THE INVENTION

[0008] In light of the above problems, an object of the presentinvention is, in a group III nitride semiconductor device, to improvethe productivity and heat radiation characteristic and, at the sametime, to improve device performance through a reduction in parasiticcapacitances.

[0009] The present invention relates to a semiconductor device whichcomprises a group III nitride semiconductor layer formed on a singlecrystalline sapphire substrate, a source electrode and a drain electrodeformed apart from each other on the surface of said group III nitridesemiconductor layer, and a gate electrode formed between said sourceelectrode and said drain electrode; wherein

[0010] said group III nitride semiconductor layer is formed on an Aplane of said single crystalline sapphire substrate.

[0011] The present invention provides a semiconductor device whichcomprises a group III nitride semiconductor layer formed on a singlecrystalline sapphire substrate, a source electrode and a drain electrodeformed apart from each other on the surface of said group III nitridesemiconductor layer, and a gate electrode formed between said sourceelectrode and said drain electrode; wherein

[0012] said group III nitride semiconductor layer is formed on an Aplane of said single crystalline sapphire substrate; and the sourceelectrode, the drain electrode and the gate electrode are formed to liealong a direction which makes an angle within 20° with a C axis of saidsingle crystalline sapphire substrate.

[0013] In the present invention, a group III nitride semiconductor layeris formed on an A plane of a single crystalline sapphire substrate. FIG.4 is a view illustrating the orientation of planes of sapphire. In thisdrawing, a (0001) plane is formed perpendicular to the C axis, and a(11-20) plane is formed to associate with a pair of lateral faces of ahexagonal prism. In the illustration, formed are two {0001} planes (Cplanes) which are equivalent to (0001), six {11-20} planes (A planes)which are equivalent to (11-20), and six {1-100} planes (M planes) whichare equivalent to (1-100), respectively. Among these planes, it is an Aplane on which a group III nitride layer is formed to construct a FET inthe present invention.

[0014] In the field of optical devices such as a semiconductor laser,there are some reports in which the technique to form a group IIInitride semiconductor layer upon an A plane of sapphire is examined. Fora GaN based optical device, too, although a C plane of a sapphiresubstrate is very often chosen as the crystal growth plane for a GaNbased semiconductor layer, a proposal to use an A plane of sapphire asthe crystal growth plane has been put forward, as described in JapanesePatent Application Laid-open No. 297495/1995.

[0015] Nevertheless, in the field of electronic devices including FETs,no attempts of forming a device on any plane other than the C plane, inparticular on a sapphire A plane, has been made, which can be attributedto the following reasons.

[0016] For a FET making use of a group III nitride semiconductor, it isimportant to utilize carriers generated by the piezoelectric effect andspontaneous polarization effectively, in device designing. Therefore,for growing an epitaxial layer, it becomes essential to use a crystalplane where the piezoelectric effect and spontaneous polarization takeplace effectively as a growth plane. In other words, in order to form anelectronic device on a plane parallel to a C axis, it becomes importantto grow a group III nitride semiconductor layer stably in the directionof the C axis. Furthermore, the growth of defects in the group IIInitride semiconductor layer leads to inefficient piezoelectric effectsthrough lattice relaxation so that defects such as dislocations need tobe reduced. While A reduction of defects is required in a certain extentin the case of semiconductor lasers or the like, in the case ofelectronic devices where the structure of semiconductor layers isconsiderably different, the level of the defect reduction required isquite different.

[0017] Yet, conventional techniques have not given any clear guideleading to a process for forming a group III nitride semiconductor layerstably in the direction of a C axis while reducing defects.

[0018] Meanwhile, a sapphire single crystal has a hexagonal crystalstructure. For instance, an A plane of sapphire has, within the plane,an anisotropy of crystal structure between the direction of the C axisand the direction perpendicular to that. In regard of the relativepermittivities, the values are 11.5 in the parallel direction to the Caxis and 9.3 in the perpendicular direction, respectively, having adifference of about 20%. Consequently, in the case that a FET is to beformed upon a plane other than a C plane, for instance, upon an A plane,required are further examinations of various aspects: whether similarperformances to those of a FET with a C plane can be obtained, whethernew problems that have not been hitherto seen in the case the formationis made upon a C plane may arise and so forth. Moreover, there isrequired sufficient knowledge in device design to achieve stablefabrication of FETs with prescribed performances, in spite ofdifficulties caused by an anisotropy of this sort. However, suchexaminations have been hardly made so far.

[0019] In the present invention, a group III nitride semiconductor layeris formed upon an A plane of sapphire to construct a FET. This providesthe following advantages.

[0020] First, parasitic capacitances in the longitudinal direction ofthe substrate can be reduced and thereby the device capability of highspeed operation can be improved.

[0021] Secondly, the device can be manufactured using a substrate with alarge diameter so that the productivity can be greatly improved.

[0022] Thirdly, as the substrate can have a superior feasibility inmechanical processing in comparison with that of the C plane sapphire,the substrate can be made thin. In practice, its thickness can be made100 μm or less, even not greater than 50 μm. As a result, heat radiationcharacteristic of the substrate can be markedly improved and besidesparasitic capacitances in the longitudinal direction of the substratecan be reduced even further.

[0023] Further, in the present invention, the layout of a FET is set insuch a way that a source electrode, a drain electrode and a gateelectrode are well aligned within a prescribed range with respect to thedirection of the C axis of sapphire, which enables the FET to operate athigh speed.

BRIEF DESCRIPTION OF THE DRAWING

[0024]FIG. 1 is a couple of cross-sectional views showing asemiconductor device according to the present invention; the lower view(b) illustrates the electric field created in a FET with a structureshown in the upper view (a), when operating.

[0025]FIG. 2 is a pair of top views showing a semiconductor deviceaccording to the present invention; the upper view (a) shows a devicewith electrodes aligned precisely along the direction of the C axis ofsapphire and the lower view (b) shows a device with electrodes alignedalong the direction tilted from the C axis by angle α.

[0026]FIG. 3 is a view in explaining the operation of the presentinvention resulting in an excellent performance of a semiconductordevice.

[0027]FIG. 4 is a view illustrating the orientation of planes in asingle crystalline sapphire.

[0028]FIG. 5 is a cross-sectional view showing a conventionalsemiconductor device with FET structure.

[0029]FIG. 6 is a cross-sectional view showing another conventionalsemiconductor device with HEMT structure.

[0030]FIG. 7 is a graphical representation showing the dependences ofthermal resistance and surface average temperature on substratethickness, obtained by simulation.

[0031]FIG. 8 is a view in explaining the device model subjected toanalysis made by simulation of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

[0032] The term “the group III nitride semiconductor” in the presentinvention refers to any semiconductor containing nitrogen as a group Velement, including a gallium nitride based semiconductor such as GaN,AlGaN, InGaN, AlGaInN, and also a semiconductor such as AlN, InN.

[0033] The present invention can be applied to either of a HEMT and aMESFET. When applied to a HEMT, it takes a structure in which a groupIII nitride semiconductor layer comprises an operation layer and anelectron supply layer formed thereon and at the interface of theselayers, a two dimensional electron gas is formed. In the presentinvention, a group III nitride semiconductor layer is formed on a planelying parallel to a C axis to construct a FET, which has not beenhitherto investigated. In order to form a group III nitridesemiconductor layer on a plane lying parallel to a C axis and fabricatestably a FET of high quality, it is important to select appropriately asubstrate surface treatment prior to the epitaxial growth, growthconditions and so on. For instance, as described below, it is effectiveto perform, as a pretreatment prior to the epitaxial growth, anannealing in oxygen or hydrogen under the condition where thetemperature is 1100° C. or higher and the duration is 30 minutes orlonger. The upper limits for the temperature and the duration can besatisfactorily set to be, for example, not higher than 1600° C. and notlonger than 120 minutes, respectively. In addition to this, a techniquesuch as to set the epitaxial growth rate in an appropriate range iseffective. With techniques aforementioned, an epitaxial growth layer ofhigh quality where the piezoelectric effect and spontaneous polarizationmay steadily take place can be obtained.

[0034] In the present invention, when the thickness of the sapphiresubstrate is set to be 100 μm or less, heat radiation characteristic ofthe substrate can be markedly improved and besides parasiticcapacitances in the longitudinal direction of the substrate can bereduced even further.

[0035] Further, in the present invention, by setting the thickness ofthe sapphire substrate to satisfy the following equation:${t_{sub} \leqq {\frac{1}{\alpha}\frac{ɛ_{sub}\quad S_{pad}}{ɛ_{epi}\quad S_{gate}}t_{act}}},$

[0036] where

[0037] S_(pad) is the area of the pad electrode;

[0038] S_(gate) is the area of the gate electrode;

[0039] ε_(sub) is the relative permittivity of the sapphire substrate inthe direction of the thickness;

[0040] ε_(epi) is the relative permittivity of the group III nitridesemiconductor layer in the direction of the thickness;

[0041] t_(sub) is the thickness of the sapphire substrate; and

[0042] t_(act) is the effective thickness of the group III nitridesemiconductor layer,

[0043] the degradation of the FET high frequency characteristic causedby parasitic capacitances that is attributed to the pad electrodes canbe suppressed. Here, the pad electrodes refer to electrodes to supplycurrent for a source or a drain from the outside. Further, t_(act) (theeffective thickness of the group III nitride semiconductor layer)represents the distance from the interface of the gate electrode and thesurface of the semiconductor layer to the layered region where carriersare accumulating. For instance, in a HEMT, this refers to the distancebetween the lower end of the gate electrode and the two-dimensionalelectron gas layer, while, in a MESFET, this refers to the thickness ofthe depletion layer under the gate electrode. Now, referring to thefigures, the point described above is explained in detail below.

[0044]FIG. 3 is a schematic view showing a structure of a GaN basedHEMT. Herein, upon a sapphire substrate 2, a GaN based semiconductorepitaxial growth layer 3 is laid and, on its surface, a gate electrode 4and a pad electrode 5 are formed. In this figure, source and drainelectrodes, interconnections and the likes are omitted. On the back faceof the sapphire substrate 2, a ground conductor layer 1 is set. The padelectrode fills the role of supplying the transistor with electric powerfed from the outside. In the transistor having such a structure,parasitic capacitances C₁ and C₂ are generated immediately under thegate electrode 4 and immediately under the pad electrode 5,respectively, as illustrated in the figure. The amounts of C₁ and C₂ canbe expressed as follows: $\begin{matrix}{C_{2} = {{ɛ_{0}\frac{ɛ_{sub}\quad ɛ_{epi}}{{ɛ_{epi}\quad t_{sub}} + {ɛ_{sub}\quad t_{epi}}}S_{pad}} \approx {ɛ_{0}\quad ɛ_{sub}\quad {S_{pad}/t_{act}}}}} & (A) \\{C_{1} = {ɛ_{0}\quad ɛ_{epi}\quad {S_{gate}/t_{act}}}} & (B)\end{matrix}$

[0045] where

[0046] S_(pad) is the area of the pad electrode 5;

[0047] S_(gate) is the area of the gate electrode 4;

[0048] ε_(sub) is the relative permittivity of the sapphire substrate 2;

[0049] ε_(epi) is the relative permittivity of the GaN basedsemiconductor epitaxial growth layer 3;

[0050] t_(sub) is the thickness of the sapphire substrate 2;

[0051] t_(epi) is the thickness of the GaN based semiconductor epitaxialgrowth layer 3; and

[0052] t_(act) is the effective thickness of the GaN based semiconductorepitaxial growth layer 3.

[0053] While the GaN based semiconductor epitaxial growth layer isnormally equal to or less than 1 μm, and for instance, within 0.02 to0.05 μm in thickness, the substrate thickness is, for example, as largeas 10 μm so that the approximation presented in Equation (A) can beaccepted. If the amount of the parasitic capacitance C₂ due to the padelectrode is made to be within 10% and preferably within 5% of theamount of the parasitic capacitance C₁ due to the gate electrode,degradation of high frequency characteristic for a transistor can besuppressed. With the condition of 10% limit being taken, thecontribution of the parasitic capacitance C₂ becomes significant, whencondition following is satisfied:

C ₂ ≧C ₁×0.1

[0054] Substituting the above Equations (A) and (B) into this equation,the following Equation (1) is given. $\begin{matrix}{t_{sub} \leqq {10\frac{ɛ_{sub}\quad S_{pad}}{ɛ_{epi}\quad S_{gate}}t_{act}}} & (1)\end{matrix}$

[0055] When a substrate thickness satisfying this equation is taken, thecontribution of the parasitic capacitance under the pad electrodebecomes significant and, thus, an application of the present inventionthat reduces the relative permittivity in the direction of the substratethickness becomes even more effective. That is, aiming at success inimproving heat radiation characteristic and reducing the parasiticcapacitances in the direction of the substrate thickness, it ispreferable to make the substrate thickness as thin as possible. However,in conventional techniques making use of a C plane of sapphire, not onlythe mechanical strength of the substrate is insufficient but also aproblem of generation of the parasitic capacitance under the padelectrode may arise if a substrate thickness satisfying Equation (1) istaken so that there is a limitation to thin the substrate. In contrast,according to the present invention which reduces the relativepermittivity in the direction of the substrate thickness, since theabsolute value of the parasitic capacitance under the pad electrode canbe lessened, the contribution of the parasitic capacitance under the padelectrode can be eliminated even if the sapphire substrate is made thin;and degradation of high frequency characteristic of the FET can be alsoprevented.

[0056] Herein, the values of respective parameters are normally in thefollowing ranges.

[0057] S_(pad)/S_(gate): 10 to 1000

[0058] ε_(sub): 9.4 to 11.4

[0059] ε_(epi): approximately 9.0

[0060] t_(sub): 10 to 600 μm (below 10 μm, a faulty operation of thetransistor may arise)

[0061] t_(act): 0.02 to 0.05 μm

[0062] Taking the above ranges of the parameters into consideration, therange where the contribution of the parasitic capacitances under the padelectrode becomes significant is expressed by

t _(sub)≦50 μm.

[0063] Similarly, if the condition of 5% limit is taken, in the range of

t _(sub)≦100 μm,

[0064] the contribution of the parasitic capacitances under the padelectrode becomes noticeable.

[0065] The above explanation is concerned with the range of thesubstrate thickness where the effects of the present invention becomemore evident, taking a HEMT as an example, but the similar holds for aMESFET. In the case of a HEMT, t_(act) is the distance between the gateelectrode and the two-dimensional electron gas layer. In the case of aMESFET, by defining t_(act) as “the thickness of the depletion layerunder the gate electrode”, the similar argument to the above can beapplied thereto, and thus Equation (1) is applicable to everytransistor. Further, as the values of respective parameters normallyemployed for a MESFET are similar to those mentioned above, the range oft_(sub) expressed by Equation (1) is also applied to every transistor.

[0066] Now, referring to the drawings, the preferred embodiments of thepresent invention are described below.

[0067]FIG. 1 is a couple of views showing a structure of an AlGaN/GaNheterojunction FET of the present embodiment. A manufacturing process ofthese FETs is described below.

[0068] First, an A plane sapphire (the basal plane is a (11-20) plane)with a diameter of 8 inches is prepared. After cleaning the substratesurface, an annealing is performed in oxygen or hydrogen under thecondition, for example, such as at the temperature of 1200° C. and for60 minutes. In addition to this annealing, an appropriated selection ofa growth rate of a semiconductor layer can make the gallium nitridebased semiconductor layer grow stably in the direction of a C axis. Thedefect density of the obtained semiconductor layer can be also maderelatively small.

[0069] The growth of the gallium nitride semiconductor layer can beconducted, for example, by the MOVPE (Metallo-Organic Vapour PhaseEpitaxy) method, as follows. First, at a low temperature of 400 to 650°C., a buffer layer 12 of AlN or GaN is formed. After raising thetemperature, an epitaxial layer 13 is grown that comprises a galliumnitride based semiconductor material, which is to constitute the FET.

[0070] Using a resist as a mask, N ions are then implanted in so as toisolate an n-layer. The implantation condition is that, for example, anaccelerating energy is 100 keV and a dose density 10¹⁴ cm⁻².

[0071] Next, after Ti and Al are laid by the lift-off technique, anannealing is carried out to form a source electrode 15, a drainelectrode 17 and a pad electrode (not shown in the drawing). Thethicknesses of Ti and Al are set to be, for example, 20 nm and 200 nm,respectively. The annealing is carried out, for example, at 650° C. for30 seconds in nitrogen atmosphere.

[0072] Next, Ni and Au are laid by the lift-off technique to form a gateelectrode 16. The thicknesses of Ni and Au are set to be, for example,20 nm and 200 nm, respectively.

[0073] Subsequently, an oxide film or a SiN film for a protective filmis grown and through holes for making contact are formed, and then, bythe step of gold plating, an interconnection section is formed. Afterthat, a wafer on which devices are formed is thinned to a thickness of10 to 50 μm by such a means as polishing, and, then, broken into chipsby dicing. In dicing, it is preferable to utilize (0001) planes and(1-100) planes. By conducting dicing after scribing along intersectionsof these planes first, dicing can be carried out relatively easily.Thereby, a FET with a structure shown in FIG. 1 can be obtained.

[0074] Now, for a high frequency FET, in order to enhance a highfrequency performance, the reduction of parasitic capacitance due to thedrain electrode, which functions as a signal output electrode, is amatter of more importance. In the present embodiment, the layout inplane of the FET is set to satisfy a prescribed condition, for thatpurpose.

[0075] The state of the electric field in a FET of the presentembodiment, when operating, is illustrated in FIG. 1(b). In FIG. 1(b), aline of electric force 18 drawn from the source to the gate correspondsto a parasitic capacitance C_(gs) between the gate and the source, whilea line of electric force 19 drawn from the drain to the gate correspondsto a parasitic capacitance C_(gd) between the gate and the drain.Further, a line of electric force 20 drawn from the source to the draincorrespond to a parasitic capacitance C_(ds) between the drain and thesource.

[0076] Meanwhile, the cut-off frequency f_(T) of the FET, dependent onthe C_(gd) and C_(ds), both of which are parasitic capacitancesattributed to the drain electrode, can be expressed approximately by thefollowing equation, when the transconductance is denoted by G_(m).

f _(T) =G _(m)/2π(C _(gd) +C _(ds))

[0077] Here, C_(gd) is dependent on the relative permittivity of theepitaxial layer 13 and hardly affected by the relative permittivity ofthe sapphire substrate 11. On the other hand, in respect of C_(ds), aline of electric force 20 corresponding to it passes through thesapphire substrate 11, and its value depends partially on the relativepermittivity of the sapphire substrate 11.

[0078] Taking the above into consideration, the present inventorsconducted device simulations for a FET having a gate length of 1 μm, asource-drain gap of 3 μm and a GaN film thickness of 0.5 μm, assumingthat relative permittivity of the substrate there for is 9.3 or 11.5. Ina model wherein the relative permittivity of the substrate was 9.3, theresulting cut-off frequency in the saturation region with V_(DD)=10 Vwas estimated to be 24.5 GHz. In the other model wherein the relativepermittivity of the substrate was 11.5, the cut-off frequency wasestimated to be 23.3 GHz, indicating clearly there was a difference ofabout 5% between these two models. In effect, the operational speedchanges by 5% with the direction in which the FET is placed on an Aplane sapphire. If the gate electrode, the source and drain electrodesare disposed to lie parallel to the C axis of sapphire, the speed of FEToperation increases by about 5%, compared with that of the case in whichthe lying direction is perpendicular thereto.

[0079] Next, the results of investigations of the relationship betweenthe layout and the performance of the FET are shown below. When theangle (the deviating angle) forming between the direction along whichthe gate electrode and the source and drain electrodes of the FET lieand the C axis of the sapphire substrate is taken as α, as shown in FIG.2(b), the relationship between α and the amount of speed reduction (theamount of speed reduction given by comparison with the speed at α=0) isas shown in the following table. TABLE 1 Deviating Angle Amount of Speedα (degree) Reduction (%) 0 0 12 0.1 16 0.2 20 0.3

[0080] As, in practice, it is desirable to keep the amount of speedreduction 0.3% or less, in other words, to make the operational speed99.7% or more of the maximum speed, the deviating angle a with respectto the direction in the layout to provide the maximum speed ispreferably set to be 20° or less.

[0081] Further, when the sapphire A plane is utilized, the anisotropy ofthe permittivity exists on the plane for device formation, which resultsin a difference in signal propagation characteristic betweenpair-transistors and becomes a factor to cause a distortion in theoperational amplifier and the like. The amount of this distortion whichis proportional to the square value of sin α has the relationship listedin the following table. TABLE 2 Deviating Angle Amount of α (degree)Distortion (%) 6 1 10 3 30 25 45 50 90 100

[0082] As in practice, it is desirable that the amount of distortion iskept to be preferably 3% or less and more preferably 1% or less, set tobe preferably 10° or less and more preferably 6° or less with a view toreducing the amount of distortion.

[0083] Accordingly, in the present embodiment, the layout in plane ofthe FET is set as shown in FIG. 2(b) and an angle α made between thedirection along which the gate electrode 16, the source 15 and drainelectrodes 16 lie and the direction of the sapphire C axis is set to bewithin 6°. The direction of the drain current is, therefore,substantially perpendicular to the sapphire C axis. Through thisarrangement, a FET with an excellent performance in high-speed operationcan be obtained.

[0084] Further, the structural relationship between a FET of the presentembodiment and the pad electrode as well as the substrate is expalned inFIG. 3. Herein, the values of respective parameters are as follows:

[0085] S_(pad)/S_(gate) is 100;

[0086] ε_(sub) is 9.4;

[0087] ε_(epi) is approximately 9.0;

[0088] t_(sub) is 10 to 100 μm; and

[0089] t_(act) is 0.02 to 0.05 μm.

[0090] As described above, the substrate thickness with which acontribution of the parasitic capacitance due to the pad electrodebecomes significant is given by the following Equation (1).$\begin{matrix}{t_{sub} \leqq {10\frac{ɛ_{sub}\quad S_{pad}}{ɛ_{epi}\quad S_{gate}}t_{act}}} & (1)\end{matrix}$

[0091] Taking the above ranges of the parameters into consideration, inan example of the present embodiment, the contribution of the padelectrode parasitic capacitance becomes significant in the range of

t _(sub)≦52 μm.

[0092] In the present embodiment, the substrate thickness is set to be10 to 50 μm from the point of view of improving heat radiationcharacteristic and reducing parasitic capacitances in the direction ofthe substrate thickness. When the device is formed on a sapphire C planeas the conventional one, with a substrate thickness of this sort, thepad electrode parasitic capacitances cause a problem. In contrast, inthe present embodiment, such a problem is solved, because an A plane ofsapphire is utilized as a plane for device formation.

EXAMPLES Example 1

[0093]FIG. 1 shows the structure of an AlGaN/GaN hetero junction FET ofthe present example. This FET was fabricated by a process whichcomprises the steps of growing a gallium nitride semiconductor layerupon an A plane sapphire substrate (the basal plane thereof is a (11-20)plane) with a diameter of 8 inches, forming electrodes and so on, andthereafter polishing to a thickness of 30 μm and then breaking intochips.

[0094] A manufacturing method was the similar one to that mentioned inDETAILED DESCRIPTION OF THE INVENTION above. An annealing after cleaningof the substrate was performed in oxygen at 1200° C. The growthtemperature for a low-temperature buffer layer was set at about 650° C.,and for other layers at about 1050° C., respectively. An epitaxial layer12 was made to have a structure wherein the following layers were laidin this order: that is

[0095] an AlN buffer layer (with a thickness of 100 μm);

[0096] a GaN layer (with a thickness of 0.5 μm);

[0097] a non-doped Al_(0.2)Ga_(0.8)N layer (with a thickness of 5 nm);

[0098] a 4×10¹⁸ cm⁻³ Si-doped Al_(0.2)Ga_(0.8)N layer (with a thicknessof 15 nm); and

[0099] a non-doped Al_(0.2)Ga_(0.8)N layer (with a thickness of 5 nm).

[0100] Further, dicing was performed by utilizing (0001) plane and(1-100) plane.

[0101] In the present example, the layout in plane of the FET was set,as shown in FIG. 2(a), where directions along which a gate electrode 15,source 15 and drain electrodes 16 lie was substantially parallel to thesapphire C axis. The direction of the drain current is, thus,substantially perpendicular to the sapphire C axis. As the orientationof the C axis within a wafer can be found out beforehand throughmeasurements of X-ray analysis or such, it can be easily recognized bymarking its direction with a notch or the like. Further, in mask design,if interconnections between FETs are laid in the direction parallel orperpendicular to that of the FETs, the area of a rectangular chip can beutilized effectively. Further, coplanar lines may be employed forinterconnections and, in such a case, it is preferable to adjustimpedances by varying spacing between lines, while taking the differencein permittivity into consideration.

[0102] Further, in a FET of the present example, the values ofafore-mentioned parameters were as follows:

[0103] S_(pad)/S_(gate) is 100;

[0104] ε_(sub) is 9.4;

[0105] ε_(epi) is approximately 9.0;

[0106] t_(sub) is 30 μm; and

[0107] t_(act) is 0.05 μm.

[0108] By substituting the above parameters into the afore-mentionedEquation (1), the range of the substrate thickness where thecontribution of the parasitic capacitances due to the pad electrodebecomes significant is given by

t _(sub)≦52 μm.

[0109] In the present example, the substrate thickness was set to be 30μm with a view of improving heat radiation characteristic and reducingparasitic capacitances in the direction of the substrate thickness. Whenthe device is formed on a sapphire C plane as the conventional one, witha substrate thickness of this sort, the pad electrode parasiticcapacitances cause a problem. In contrast with this, in the presentexample, such a problem is solved, because an A plane of sapphire isutilized as the plane for device formation.

[0110] A FET obtained in the present example demonstrated to haveexcellent productivity, heat radiation characteristic and performance inhigh speed operation.

Reference Example 1

[0111] Subjecting a HEMT shown in FIG. 8 to analysis where a GaN basedsemiconductor layer 81 is formed upon a sapphire substrate 80 and asource electrode 82, a gate electrode 83 and a drain electrode 84 areformed thereon, the dependences of thermal resistance and surfaceaverage temperature on substrate thickness were obtained by simulation.The calculated results are shown in FIG. 7. The thermal resistance andsurface average temperature each decrease with decreasing the substratethickness, and show a marked decrease, especially in the region ofthickness of 50 μm or less. These results confirm that, by setting thethickness of the sapphire substrate to be 50 μm or less, a noticeableeffect to heat radiation can be attained.

Reference Example 2

[0112] A sapphire substrate with a thickness of 300 μm wherein an Aplane was set to be the basal plane and another sapphire substrate witha thickness of 300 μm wherein a C plane was set to be the basal planewere prepared, and, after grinding, close inspection of their aspectswere conducted. In the sapphire substrate wherein a C plane was set tobe the basal plane, cracks appeared when its thickness became 70 μm orso. In contrast with this, in the sapphire substrate wherein an A planewas set to be the basal plane, cracks did not appear, even when thesubstrate thickness became as thin as 30 μm, showing nothing abnormal inappearance.

Summary of Disclosure

[0113] As set forth above, in the present invention, upon an A plane ofa single sapphire substrate, a group III nitride semiconductor layer isformed to construct a FET. This makes it possible to provide a goodproductivity as well as to improve heat radiation characteristic.Further, as the layout in plane of the FET is selected to satisfy aprescribed condition, a good performance in high speed operation can beachieved.

What we claim is:
 1. A semiconductor device which comprises a group IIInitride semiconductor layer formed on a single crystal sapphiresubstrate, a source electrode and a drain electrode formed apart fromeach other on the surface of said group III nitride semiconductor layer,and a gate electrode formed between said source electrode and said drainelectrode; wherein said group III nitride semiconductor layer is formedon an A plane of said single crystalline sapphire substrate; and thesource electrode, the drain electrode and the gate electrode are formedto lie along a direction which makes an angle within 20° with a C axisof said single crystalline sapphire substrate.
 2. A semiconductor deviceaccording to claim 1, wherein said group III nitride semiconductor layercomprises an operation layer and an electron supply layer formedthereon, and a two-dimensional electron gas is formed at the interfaceof these layers.
 3. A semiconductor device according to claim 1 or 2,wherein a thickness of said sapphire substrate is 100 μm or less.